" Laboratory of Digital Systems and Computer Architecture
All my publications are online and can be accessed through: Minas Dasygenis
Journal Publications

Journal Publications (in Well known International Journals with review) :

  • [Γ1] M. Dasygenis, I. Karafyllidis and A. Thanailakis, “A single-electron XOR gate”,Microelectronics Journal, vol. 32, pp. 117-119, (2001).
  • [Γ2] D. Soudris, M. Dasygenis and A. Thanailakis, "VLSI methodology for the design of RNS and QRNS full addder based Converters," in IEE Proceedings-Circuits, Devices, and Systems, Vol. 149, No. 4, pp. 241-250, (2002).
  • [Γ3] M. Dasygenis , N. Kroupis, K. Tatas, A. Argyriou, D. Soudris and A. Thanailakis, “Power and performance exploration of embedded systems executing multimediakernels”. in IEE Proceedings-Computer and Digital Techniques, Vol. 149, No.4, pp.164-172, (2002).
  • [Γ4] K. Tatas, M. Dasygenis , N. Kroupis, A. Argyriou, D. Soudris, A. Thanailakis,“Data Memory Power Optimization and Performance Exploration of EmbeddedSystems for Implementing Motion Estimation Algorithms”, Real-Time Imaging, Vol.9, No 6, pp. 371-386, Special Issue on Software Engineering of Real-time ImagingSystems, Elsevier science, (2003).
  • [Γ5] N. Kroupis, M.Dasygenis, D. Soudris, A. Thanailakis, “A Modified Spiral Search Algorithm and its embedded System Architecture Design”, International Journal ofInformation Technology, Enformatica, Vol. 2, No. 3, ISSN 1305-2403, pp. 199-205,(2005).
  • [Γ6] M. Dasygenis, E. Brockmeyer, B. Durinck, F. Catthoor, D. Soudris and Α. Thanailakis, “A Combined DMA and Application Specific Prefetching Approach forTackling the Memory Latency Bottleneck”, IEEE Transactions on VLSI, Vol. 14, No. 3, ISSN 1063-8210, pp. 279-291, (2006).
  • [Γ7] N. Kroupis, N. Zervas, M.Dasygenis , K. Tatas, A. Argyriou, D. Soudris, and A.Thanailakis, “Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors”, Springer Science, Journal of VLSI Signal Processing Systems, Vol. 44, Issue 1-2, ISSN:0922-5773, pp. 153-171, (2006).
  • [Γ8] M. Dasygenis, K. Mitroglou, D. Soudris and A. Thanailakis, “A Full-Adder-based Methodology for the Design of Scaling Operation in Residue Number System”,accepted for publication on IEEE Transactions on Circuits and Systems I (2007).
Conference Publications

Selected Conference Publications (in International Conferences after review) :

  • [Δ1] D. Soudris, M. Dasygenis, and A. Thanailakis, “Designing RNS and QRNS FullAdder Based Converters”, Proc. of Int. Symp. on Circuits and Systems (ISCAS),Geneva, Switzerland, pp. II-20 - II-23, (2000).
  • [Δ3] D. Soudris, N. Zervas, A. Argyriou, M. Dasygenis , K. Tatas, C. Goutis and A.Thanailakis, “Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications”, Proc. of the 10th Int. Workshop Power And TimingModelling, Optimization And Simulation (PATMOS), Gottigen, Germany, pp. 243-254, (2000).
  • [Δ4] K.Tatas, A. Argyriou, M. Dasygenis , N. Zervas, and D. Soudris, “Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores”, Proc. of the 2 nd IEEE International Symposium on Quality Electronic Design(ISQED), San Jose, California, USA, pp. 456-461, (2001).
  • [Δ5] M. Dasygenis, D. Soudris, S. Vasilopoulou and A. Thanailakis, “A CAD tool for automatic generation of RNS and QRNS converters”, In Proc. of First Conference onMicroelectronics Microsystems Nanotechnology (MMN), Athens, pp. 297-300,(2000).
  • [Δ6] M.Dasygenis, N. Kroupis, A. Argyriou, K. Tatas, N. Zervas and D. Soudris, “Data and Instruction Memory Exploration of Embedded Systems for Multimedia Applications”, Proc. of IEEE 2001 Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), Salt Lake City, Utah, (2001).
  • [Δ8] M. Dasygenis , N. Kroupis, A. Argyriou, K. Tatas, D. Soudris, N. Zervas, and A. Thanailakis, “A Memory Management Approach For Efficient Implementation Of Multimedia Kernels On Programmable Architectures”, Proc. of IEEE ComputerSociety Annual Workshop on VLSI (WVLSI), Orlando Florida, USA, pp. 171-176,(2001).
  • [Δ9] K. Tatas, M. Dasygenis , A. Argyriou, N. Kroupis, D. Soudris and A.Thanailakis, “Address Bus Power Exploration in Programmable Processors for Realization of Multimedia Applications”, Proc. of IEEE International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), Yverdon-Les-Bains, Switzerland, pp. 10.2.1-10.2.10, (2001).
  • [Δ10] N. Kroupis, M. Dasygenis , A. Argyriou, K. Tatas, D. Soudris, A. Thanailakis, N. Zervas, and C.E. Goutis, “Power, Performance and Area Exploration of Block Matching Algorithms Mapped on Programmable Processors”, IEEE Int. Conference on Image processing (ICIP), Thessaloniki, Greece, pp. 728-731, (2001).
  • [Δ14] M. Dasygenis, E. Brockmeyer, D. Soudris, F. Catthoor, A. Thanailakis, and G. Papakostas, “Performance and Energy Optimization of Multimedia Applications using DMA Combined with Prefetch”, In Proc. of Workshop on Compilers and Operating Systems for Low Power (COLP), in conjunction with PACT03 International Conference on Parallel Architectures and Compilation Techniques, New Orleans, USA, (2003).
  • [Δ15] Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, and Antonios Thanailakis, “Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications”, Proceedings of Systems,Architectures, MOdeling, and Simulation (SAMOS IV), LNCS, Volume 3133, Samos,Greece, pp. 540-549, (2004).
  • [Δ16] Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris and Antonios Thanailakis, “A Memory Hierarchical Layer Assigning andPrefetching Technique to Overcome the Memory Performance/Energy Bottleneck”, Design Automation and Test in Europe (DATE), ISBN 0-7695-2288-2, Volume 2,Munich, Germany, pp. 946-947, (2005).
  • [Δ18] Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris and Antonios Thanailakis, “Improving the Memory Bandwidth Utilization Using Loop Transformations”, Proc. of IEEE International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), Leuven, Belgium, (2005).
  • [Δ20] Minas Dasygenis, “A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration”, Design and Technology of Integrated Systems in the Nanoscale Era, Santorini (2014).
  • [Δ22] Angelos Ntasios and Minas Dasygenis, “Design, Implementation and Verification of a Customizing IP Soft Core With FPU Support”, Panhellenic Conference of Informatics, Athens, (2014).
  • [Δ23] Minas Dasygenis and Panagiotis Michailidis, “Evaluating modern parallelization techniques on block matching algorithms”, Panhellenic Conference of Informatics, Athens, (2014).
  • [Δ25] Konstantinos Anastasiou and Minas Dasygenis, “Design and Implementation of a hybrid personal response system”, Electrical and Computer Engineering Student Conference (ECESCON7), Thessaloniki, (2014).
  • [Δ26] Partonas Alexandros and Minas Dasygenis , “Design of networking game in the iPhone iOS platform”, Electrical and Computer Engineering Student Conference (ECESCON7), Thessaloniki, (2014).
  • [Δ29] Giannis Petrousov and Minas Dasygenis “A unique network EDA tool to create optimized ad hoc binary to residue number system converters”, IEEE International Conference on Power and Timing Modelling, Optimization and Simulation (PATMOS), Palma de Mallorca, Spain, (2014).