Decoder n to 2^n HDL Generator

Number of input bits (anonymous users are restricted to 6 bits):

Number of Test Vectors to generate:

Create normal decoder
Create inverted decoder

Use enabling bit
Do not use enabling bit

Use buffered input/output
Do not use buffered input/output

Inputs per gate:

Pipeline level (0: disable, 1:max,2:medium,3+ lower pipeline level):

Create VHDL, Dot file & Schematic
Create VHDL only

An archive full of HDL decoders is available here. Inside the archive, you will find: (a) the VHDL files, (b) the library file for every decoder, the report file for every decoder (output of the tool, with statistics), a summary file that prints the testbench outcome.

The filenames have the following naming convention: decoder_a_b_c_d_e_f , where a: normal (0), inverted(1), b: no enabling bit (0), enabling bit, c: input bits, d:maximum number of input ports per gate, e: pipeline level (0: no pipeline), f: do not use buffered IO (0), or use buffered IO (1).