Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.3 (WebPack) - O.76xd Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s700a
Project ID (random number) f33e745fb4b141ad9563317891462ee6.80EA397ACA6240EA8ECBB82ADD1CB027.1 Target Package: fg484
Registration ID __0_0_0 Target Speed: -4
Date Generated 2012-05-09T22:03:34 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz CPU Speed 3044 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Multiplexers=3
  • 1-bit 4-to-1 multiplexer=2
  • 8-bit 3-to-1 multiplexer=1
Registers=111
  • Flip-Flops=111
MiscellaneousStatistics
  • AGG_BONDED_IO=30
  • AGG_IO=30
  • AGG_SLICE=116
  • NUM_4_INPUT_LUT=195
  • NUM_BONDED_IBUF=12
  • NUM_BONDED_IOB=18
  • NUM_BUFGMUX=1
  • NUM_CYMUX=39
  • NUM_DP_RAM=16
  • NUM_LUT_RT=2
  • NUM_RAM32=52
  • NUM_RAMB16BWE=1
  • NUM_SHIFT=2
  • NUM_SLICEL=81
  • NUM_SLICEM=35
  • NUM_SLICE_FF=108
  • NUM_XOR=37
NetStatistics
  • NumNets_Active=293
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=10
  • NumNodesOfType_Active_BRAMDUMMY=18
  • NumNodesOfType_Active_CLKPIN=92
  • NumNodesOfType_Active_CNTRLPIN=102
  • NumNodesOfType_Active_DOUBLE=603
  • NumNodesOfType_Active_DUMMY=667
  • NumNodesOfType_Active_DUMMYBANK=7
  • NumNodesOfType_Active_DUMMYESC=16
  • NumNodesOfType_Active_GLOBAL=33
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_HUNIHEX=39
  • NumNodesOfType_Active_INPUT=844
  • NumNodesOfType_Active_IOBOUTPUT=16
  • NumNodesOfType_Active_OMUX=245
  • NumNodesOfType_Active_OUTPUT=247
  • NumNodesOfType_Active_PREBXBY=228
  • NumNodesOfType_Active_VFULLHEX=17
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=30
  • NumNodesOfType_Gnd_BRAMDUMMY=5
  • NumNodesOfType_Gnd_DOUBLE=6
  • NumNodesOfType_Gnd_DUMMY=8
  • NumNodesOfType_Gnd_INPUT=16
  • NumNodesOfType_Gnd_OMUX=9
  • NumNodesOfType_Gnd_OUTPUT=5
  • NumNodesOfType_Gnd_PREBXBY=3
  • NumNodesOfType_Vcc_BRAMDUMMY=5
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_INPUT=13
  • NumNodesOfType_Vcc_PREBXBY=5
  • NumNodesOfType_Vcc_VCCOUT=13
SiteStatistics
  • IBUF-DIFFSTB=1
  • IOB-DIFFMLR=6
  • IOB-DIFFMTB=4
  • IOB-DIFFSLR=5
  • IOB-DIFFSTB=3
  • SLICEL-SLICEM=20
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=12
  • IBUF_DELAY_ADJ_BBOX=12
  • IBUF_INBUF=12
  • IBUF_PAD=12
  • IOB=18
  • IOB_DELAY_ADJ_BBOX=4
  • IOB_INBUF=4
  • IOB_OUTBUF=18
  • IOB_PAD=18
  • RAMB16BWE=1
  • RAMB16BWE_RAMB16BWE=1
  • SLICEL=81
  • SLICEL_CYMUXF=22
  • SLICEL_CYMUXG=17
  • SLICEL_F=62
  • SLICEL_F5MUX=9
  • SLICEL_FFX=34
  • SLICEL_FFY=45
  • SLICEL_G=63
  • SLICEL_GNDF=13
  • SLICEL_GNDG=9
  • SLICEL_XORF=18
  • SLICEL_XORG=19
  • SLICEM=35
  • SLICEM_BYINVOUTUSED=8
  • SLICEM_BYOUTUSED=8
  • SLICEM_DIGUSED=8
  • SLICEM_F=35
  • SLICEM_F5MUX=26
  • SLICEM_F6MUX=8
  • SLICEM_FFX=12
  • SLICEM_FFY=17
  • SLICEM_G=35
  • SLICEM_WSGEN=35
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:12]
  • IBUF_DELAY_VALUE=[DLY0:12]
  • IFD_DELAY_VALUE=[DLY0:12]
  • SEL_IN=[SEL_IN:12] [SEL_IN_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS33:12]
  • PULL=[PULLUP:6] [PULLDOWN:5]
IOB
  • O1=[O1_INV:0] [O1:18]
  • T1=[T1_INV:0] [T1:4]
IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:4]
  • IBUF_DELAY_VALUE=[DLY0:4]
  • IFD_DELAY_VALUE=[DLY0:4]
  • SEL_IN=[SEL_IN:4] [SEL_IN_INV:0]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:18]
  • SUSPEND=[3STATE:18]
  • TRI=[TRI_INV:0] [TRI:4]
IOB_PAD
  • DRIVEATTRBOX=[8:18]
  • IOATTRBOX=[LVCMOS33:18]
  • SLEW=[SLOW:18]
RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:0] [WEB0_INV:1]
  • WEB1=[WEB1:0] [WEB1_INV:1]
  • WEB2=[WEB2_INV:1] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:1]
RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • DATA_WIDTH_A=[18:1]
  • DATA_WIDTH_B=[0:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:0] [WEB0_INV:1]
  • WEB1=[WEB1:0] [WEB1_INV:1]
  • WEB2=[WEB2_INV:1] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:1]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
SLICEL
  • BX=[BX_INV:0] [BX:18]
  • BY=[BY:21] [BY_INV:1]
  • CE=[CE:12] [CE_INV:8]
  • CIN=[CIN_INV:0] [CIN:17]
  • CLK=[CLK:56] [CLK_INV:0]
  • SR=[SR:32] [SR_INV:4]
SLICEL_CYMUXF
  • 0=[0:22] [0_INV:0]
  • 1=[1_INV:0] [1:22]
SLICEL_CYMUXG
  • 0=[0:17] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:9] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:3] [CE_INV:8]
  • CK=[CK:34] [CK_INV:0]
  • D=[D:34] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:34]
  • FFX_SR_ATTR=[SRLOW:34]
  • LATCH_OR_FF=[FF:34]
  • REV=[REV_INV:0] [REV:5]
  • SR=[SR:24] [SR_INV:4]
  • SYNC_ATTR=[ASYNC:6] [SYNC:28]
SLICEL_FFY
  • CE=[CE:11] [CE_INV:7]
  • CK=[CK:45] [CK_INV:0]
  • D=[D:44] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:43] [INIT1:2]
  • FFY_SR_ATTR=[SRLOW:45]
  • LATCH_OR_FF=[FF:45]
  • REV=[REV_INV:0] [REV:5]
  • SR=[SR:21] [SR_INV:4]
  • SYNC_ATTR=[ASYNC:18] [SYNC:27]
SLICEL_XORF
  • 1=[1_INV:0] [1:18]
SLICEM
  • ALTDIG=[ALTDIG:8] [ALTDIG_INV:0]
  • BX=[BX_INV:0] [BX:28]
  • BY=[BY:35] [BY_INV:0]
  • CE=[CE:8] [CE_INV:0]
  • CLK=[CLK:35] [CLK_INV:0]
  • SR=[SR:25] [SR_INV:10]
SLICEM_BYINVOUTUSED
  • 0=[0:8] [0_INV:0]
SLICEM_BYOUTUSED
  • 0=[0:8] [0_INV:0]
SLICEM_DIGUSED
  • 0=[0:8] [0_INV:0]
SLICEM_F
  • DI=[DI:35] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:8] [SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:35]
SLICEM_F5MUX
  • S0=[S0:26] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:8] [S0_INV:0]
SLICEM_FFX
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:12] [CK_INV:0]
  • D=[D:12] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:12]
  • FFX_SR_ATTR=[SRLOW:12]
  • LATCH_OR_FF=[FF:12]
  • SYNC_ATTR=[ASYNC:12]
SLICEM_FFY
  • CE=[CE:8] [CE_INV:0]
  • CK=[CK:17] [CK_INV:0]
  • D=[D:17] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:17]
  • FFY_SR_ATTR=[SRLOW:17]
  • LATCH_OR_FF=[FF:17]
  • SYNC_ATTR=[ASYNC:17]
SLICEM_G
  • DI=[DI:35] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:8] [SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:35]
SLICEM_WSGEN
  • CK=[CK:35] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:27]
  • WE=[WE_INV:10] [WE:25]
  • WE0=[WE0:26] [WE0_INV:0]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=12
  • PAD=12
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=12
  • SEL_IN=12
IBUF_INBUF
  • IN=12
  • OUT=12
IBUF_PAD
  • PAD=12
IOB
  • I=4
  • O1=18
  • PAD=18
  • T1=4
IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=4
  • SEL_IN=4
IOB_INBUF
  • IN=4
  • OUT=4
IOB_OUTBUF
  • IN=18
  • OUT=18
  • TRI=4
IOB_PAD
  • PAD=18
RAMB16BWE
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • SSRA=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
RAMB16BWE_RAMB16BWE
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • SSRA=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
SLICEL
  • BX=18
  • BY=22
  • CE=20
  • CIN=17
  • CLK=56
  • COUT=17
  • F1=61
  • F2=61
  • F3=55
  • F4=22
  • G1=62
  • G2=61
  • G3=56
  • G4=16
  • SR=36
  • X=24
  • XQ=34
  • Y=23
  • YQ=45
SLICEL_CYMUXF
  • 0=22
  • 1=22
  • OUT=22
  • S0=22
SLICEL_CYMUXG
  • 0=17
  • 1=17
  • OUT=17
  • S0=17
SLICEL_F
  • A1=58
  • A2=61
  • A3=55
  • A4=22
  • D=62
SLICEL_F5MUX
  • F=9
  • G=9
  • OUT=9
  • S0=9
SLICEL_FFX
  • CE=11
  • CK=34
  • D=34
  • Q=34
  • REV=5
  • SR=28
SLICEL_FFY
  • CE=18
  • CK=45
  • D=45
  • Q=45
  • REV=5
  • SR=25
SLICEL_G
  • A1=60
  • A2=61
  • A3=56
  • A4=16
  • D=63
SLICEL_GNDF
  • 0=13
SLICEL_GNDG
  • 0=9
SLICEL_XORF
  • 0=18
  • 1=18
  • O=18
SLICEL_XORG
  • 0=19
  • 1=19
  • O=19
SLICEM
  • ALTDIG=8
  • BX=28
  • BY=35
  • BYINVOUT=8
  • BYOUT=8
  • CE=8
  • CLK=35
  • DIG=8
  • F1=35
  • F2=35
  • F3=35
  • F4=35
  • F5=16
  • FXINA=8
  • FXINB=8
  • G1=35
  • G2=35
  • G3=35
  • G4=35
  • SLICEWE1=16
  • SR=35
  • X=8
  • XQ=12
  • Y=8
  • YQ=17
SLICEM_BYINVOUTUSED
  • 0=8
  • OUT=8
SLICEM_BYOUTUSED
  • 0=8
  • OUT=8
SLICEM_DIGUSED
  • 0=8
  • OUT=8
SLICEM_F
  • A1=35
  • A2=35
  • A3=35
  • A4=35
  • D=35
  • DI=35
  • WF1=34
  • WF2=34
  • WF3=34
  • WF4=34
  • WS=35
SLICEM_F5MUX
  • F=26
  • G=26
  • OUT=26
  • S0=26
SLICEM_F6MUX
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEM_FFX
  • CE=1
  • CK=12
  • D=12
  • Q=12
SLICEM_FFY
  • CE=8
  • CK=17
  • D=17
  • Q=17
SLICEM_G
  • A1=35
  • A2=35
  • A3=35
  • A4=35
  • D=35
  • DI=35
  • WG1=34
  • WG2=34
  • WG3=34
  • WG4=34
  • WS=35
SLICEM_WSGEN
  • CK=35
  • WE=35
  • WE0=26
  • WE1=16
  • WSF=35
  • WSG=35
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700a-fg484-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700a-fg484-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 6 5 0 0 0 0 0
bitgen 7 7 0 0 0 0 0
bitinit 1 1 0 0 0 0 0
elfcheck 5 5 0 0 0 0 0
libgen 6 5 0 0 0 0 0
map 13 9 0 0 0 0 0
ngcbuild 5 5 0 0 0 0 0
ngdbuild 15 15 0 0 0 0 0
par 8 7 1 0 0 0 0
platgen 2 2 0 0 0 0 0
psf2Edward 1 1 0 0 0 0 0
trce 6 6 0 0 0 0 0
xdsgen 1 1 0 0 0 0 0
xps 4 1 0 0 0 0 0
xst 29 29 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=Modelsim-PE VHDL PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-05-09T22:02:13
PROP_intWbtProjectID=80EA397ACA6240EA8ECBB82ADD1CB027 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Spartan3A and Spartan3AN
PROP_DevDevice=xc3s700a PROP_DevFamilyPMName=spartan3a
PROP_DevPackage=fg484 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=3
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=34 NGDBUILD_NUM_FDE=19 NGDBUILD_NUM_FDR=35
NGDBUILD_NUM_FDRE=9 NGDBUILD_NUM_FDRSE=10 NGDBUILD_NUM_FDS=2 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=11 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_IOBUF=4 NGDBUILD_NUM_LUT1=2
NGDBUILD_NUM_LUT2=13 NGDBUILD_NUM_LUT3=73 NGDBUILD_NUM_LUT4=37 NGDBUILD_NUM_MUXCY=39
NGDBUILD_NUM_MUXF5=9 NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_RAM16X1D=8 NGDBUILD_NUM_RAM32X1S=10
NGDBUILD_NUM_RAM64X1S=8 NGDBUILD_NUM_RAMB16BWE=1 NGDBUILD_NUM_SRL16=2 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=37
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=34 NGDBUILD_NUM_FDE=19 NGDBUILD_NUM_FDR=35
NGDBUILD_NUM_FDRE=9 NGDBUILD_NUM_FDRSE=10 NGDBUILD_NUM_FDS=2 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=15 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=2
NGDBUILD_NUM_LUT2=13 NGDBUILD_NUM_LUT3=73 NGDBUILD_NUM_LUT4=37 NGDBUILD_NUM_MUXCY=39
NGDBUILD_NUM_MUXF5=9 NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_OBUFT=4 NGDBUILD_NUM_PULLDOWN=5
NGDBUILD_NUM_PULLUP=6 NGDBUILD_NUM_RAM32X1S=10 NGDBUILD_NUM_RAM64X1S=8 NGDBUILD_NUM_RAMB16BWE=1
NGDBUILD_NUM_SRLC16E=2 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=37
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s700a-4-fg484 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5